Semiconductor chips or wafers are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region side by side in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the source and drain regions by a thin gate oxide layer, with small portions of the source and drain regions, referred to as "extensions", directly underlying the gate. This generally-described structure cooperates to function as a transistor.
As the dimensions of MOSFETs desirably are reduced as discussed above, it will be readily appreciated that the depth to which the source and drain extensions of a transistor penetrates the silicon substrate decreases. Unfortunately, very shallow source/drain extensions are characterized by relatively high series resistances measured laterally across the extensions (i.e., measured in a dimension that is orthogonal to the depth of the extension in the substrate), which is a major cause of drive current degradation in ULSI transistors. Moreover, the shallow extensions increase the difficulty of forming otherwise desirable silicide in the source and drain regions.
To address the above-noted problem, elevated source and drain regions that are formed next to the gate on top of the substrate have been proposed. The elevated source and drain structures, however, have heretofore been formed by epitaxy, which is a high temperature process for depositing pure silicon on the substrate to establish the elevated source and drain regions. Indeed, epitaxy typically requires a deposition temperature of in excess of 1100.degree. C. As recognized herein, the use of such a high temperature degrades the profiles of dopant implants and, hence, degrades transistor performance. Further, epitaxy is an expensive process to undertake. The present invention recognizes and addresses one or more of the above-noted problems.